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May 1997
ML4828* BiCMOS Phase Modulation/Soft Switching Controller
GENERAL DESCRIPTION
The ML4828 is a complete BiCMOS phase modulation control IC suitable for full bridge soft switching converters. Unlike conventional PWM circuits, the phase modulation technique allows for zero voltage switching (ZVS) transitions and square wave drive across the transformer. The IC modulates the phases of the two sides of the bridge to control output power. The ML4828 can be operated in either voltage or current mode. Both cycle-by-cycle current limit, integrating fault detection, and soft start reset are provided. The undervoltage lockout circuit features a 1.5V hysteresis with a low starting current to allow off-line start up with a bleed resistor. A shutdown function powers down the IC, putting it into a low quiescent state. The circuit can be operated at frequencies up to 1MHz. The ML4828 contains four high current CMOS outputs which feature high slew rate with low cross conduction.
FEATURES
s s s s s s s
5V BiCMOS for low power and high frequency (1MHz) operation Full bridge phase modulation zero voltage switching circuit with independent programmable delay times Current or voltage mode operation capability Cycle-by-cycle current limiting with integrating fault detection and restart delay Can be externally synchronized Four 3 CMOS output drivers Under-voltage lockout circuit with 1.5V hysteresis
*Some Packages Are End Of Life
BLOCK DIAGRAM
VCC 14 VREF 5 SYNC RT 6 3 CT 4
2.5V REF SDN 19 UVLO
OSC DRIVER 18 A1
EA+ 10 EA- EAO 9 8
+ -
ERROR AMP
ISS Q
DELAY A
- +
MOD
T Q DRIVER 16 A2
RAMP 11 SS 7 2.5V 1.25V
Q
S R DRIVER 15 B1
+
Q
-
Q
R RST 12 ILIM IRST FAULT LOGIC S
DELAY B
Q
DRIVER
13 B2
ILIM 20 1V
+ -
17 GND
1 RA
2 RB
1
ML4828
PIN CONNECTION
ML4828 20-Pin DIP (P20) 20-Pin SOIC (S20)
RA RB RT CT REF SYNC SS EA0 EA- EA+
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
ILIM SDN A1 GND A2 B1 VCC B2 RST RAMP
TOP VIEW
PIN DESCRIPTION
PIN NAME DESCRIPTION PIN NAME DESCRIPTION
1 2 3 4 5 6 7 8 9 10
RA RB RT CT REF SYNC SS EAO EAEA+
A1 and A2 delay programming resistor. B1 and B2 delay programming resistor . Oscillator charge current programming resistor. Oscillator timing capacitor. 2.5V reference voltage. Synchronization input to oscillator. Soft start capacitor connection. Error amplifier output. Error amplifier inverting input. Error amplifier non-inverting input.
11 12 13 14 15 16 17 18 19 20
RAMP RST B2 VCC B1 A2 GND A1 SHDN ILIMIT
RC network for phase modulator ramp input. RC network for reset and integrating fault detect. B2 driver output. Power supply B1 driver output. A2 driver output. Ground. A1 driver output. Active low device shutdown. Current limit control input
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ML4828
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC .................................................................................................. 7V Output Current, Source or Sink (A1, A2, B1, B2) Pulse (0.5 s) ......................................................... 1.0A Analog Inputs (EA+, EA-, EAO, RST, RAMP, RST)............................ -0.3V to VCC + 0.3V RT Source Current .................................................... -1mA Error Amplifier Output Current ................................ 2mA Soft Start Discharge Current ...................................... 5mA CT Charging Current ................................................. -1mA Junction Temperature .............................................. 150C Storage Temperature Range ...................... -65C to 150C Lead Temperature (Soldering 10 sec.) ...................... 260C Thermal Resistance (JA) Plastic DIP ........................................................ 67C/W Plastic SOIC ..................................................... 95C/W
OPERATING CONDITIONS
Temperature Range ML4828CX ................................................. 0C to 70C ML4828IX ............................................... -40C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RA = RB = 33.3k, RT = 16k, CT = 270PF, VCC = 5V, TA = Operation Temperature Range (Notes 1,2)
PARAMETER OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation CT Discharge Current Ramp Peak Ramp Valley REFERENCE Initial Accuracy Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability Short Circuit Current ERROR AMPLIFIER Input Offset Voltage Input Common-Mode Range Open Loop Gain PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth Slew Rate 1V < VO < 2.7V 4.5V < VCC < 6.5V VO = 0.5V VO= 2.7V ISOURCE = -500A ISINK = 500A 7 5 -20 0 60 60 1.2 -0.35 2.6 80 80 1.9 -1.1 2.85 0.1 10 10 0.2 20 1.75 mV V dB dB mA mA V V MHz V/s Line, Load, & Temp TJ = 125C, 1000 hrs VREF = 0V -10 2.44 5 -23 TA = 25C, IO = 250A 4.5V < VCC < 6.5V 100A to 1mA 2.475 2.5 0.2 0.5 0.45 2.54 25 -35 2.525 1 6 V %/V mV % V mV mA Line, temp. VCT = 2V 325 1.15 1.5 2.6 1.12 TA = 25C 4.5V < VCC < 5.5V 340 360 4 2 400 380 5.3 kHz %/V % kHz mA V V CONDITIONS MIN TYP. MAX UNITS
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ML4828
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER PHASE MODULATOR EAO Zero Duty Cycle Threshold RAMP Delay to Output RAMP Discharge Current SOFT-START Charge Current Discharge Current CURRENT LIMIT/SHUTDOWN Current Limit Threshold Pin 20 Delay to Output Pin 12 Shutdown Threshold Pin 12 Restart Threshold Pin 12 Charging Current SDN Shutdown Threshold OUTPUT Output Low Level Output High Level Rise/Fall Time ZVS Programmable Delay Delay Mismatch RA/RB Reference Voltage UNDER VOLTAGE LOCKOUT Start Threshold Stop Threshold SUPPLY Start Up Current Shutdown Current ICC
Note 1: Note 2:
CONDITIONS
MIN
TYP.
MAX
UNITS
VRT = 0V
0
0.5 50
0.9 80 95
V ns mA
48
VSS = 4V VSS = 1V 6
-25 10
-50 13.2
A mA
0.9 (Note 1) 1.0 2.2 -350 1.05
1.0 50 1.1 2.4 -460 1.6
1.1
V ns
1.5 2.6 -550 2.05
V V A V
IOUT = 20 mA IOUT = 100 mA IOUT = -20 mA IOUT = -100 mA CL = 1000pF, (Note 1) 240 4.9 4.6
0.01 0.1 4.95 4.7 5 280 0 2.45 2.5
0.1 0.3
V V V V
7 315
ns ns ns
2.55
V
5.1 4.1
5.85 4.2
6.6 4.3
V V
VCC < 6V
0.6 100
1 500 7
mA A mA
VCC = 5V, CL = 1000pF, TA = 25C
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. VCC must be brought above the UVLO start voltage (6V) before dropping to VCC = 5V to ensure start-up.
5
4
ML4828
FUNCTIONAL DESCRIPTION
PHASE MODULATOR The ML4828 controls the power of a full bridge power section by modulating the phases of the switches of the A and B sides (Figure 1). The power cycle starts with A2 and B1 high, as shown in the timing diagram (Figure 2). 1. With A2 and B1 high, Q1 and Q2 are ON. Current flows through the primary of the transformer, and power is delivered to the output through the secondary winding (not shown). 2. After either the MOD or ILIM comparator trips, B1 goes low, turning off Q2. Energy in the primary winding charges the parasitic capacitances of Q2 and Q3 to +VIN during tDB. 3. B2 goes high after time tDB, which is set by the resistor connected from RB (pin 2) to GND. tDB should be set large enough such that the source of Q3 has been charged to +VIN. At this time, Q3 turns on at zero voltage. The transformer is now effectively shorted through Q1 and Q3, with the primary magnetizing current circulating in the loop formed by the transformer primary, Q1, and Q3. 4. CLOCK then goes high and A2 goes low, while A1 remains low for time tDA, which is set by the resistor connected from RA (pin 1) to GND. During this time, both Q1 and Q4 are OFF. The primary magnetizing current discharges the parasitic capacitances of Q1 and Q4 to GND. 5. A1 goes high after time tDA. At this point, the drain of Q4 is discharged to GND, and Q4 turns on at zero voltage. With both Q3 and Q4 ON, a new power cycle starts, and power is delivered to the output. The above sequence is then repeated with the roles of side A and B interchanged. The ML4828 can also be used in current mode by sensing the load current on the RAMP input (pin 11).
+VIN Q3 Q1 TA
A2
B2
TB
B1
LLEAKAGE B Q2 A TRANSFORMER Q4 TA
ML4828
A1 ILIM TB
RSENSE
Figure 1. Simplified diagram of Phase Modulated power Outputs.
CT
CLOCK
A2 tDA A1 tDA B1 tPD1 B2 tDB B tPD1 tDB tDB tDA tPD1
A
Figure 2. Phase Modulation control waveforms (Shaded areas indicate a power cycle).
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ML4828
SETTING THE OSCILLATOR FREQUENCY The ML4828 switching frequency is determined by the charge and discharge times of the network connected to the RT and CT pins. Figure 3 shows the relationships between the internal clock and the charge and discharge times.
RAMP PEAK 2.5V RAMP VALLEY 1.25V tCHARGE tDISCHARGE INTERNAL CLOCK GAIN
ERROR AMPLIFIER The ML4828 error amplifier has a 10MHz bandwidth and a 10V/s slew rate. Figure 4 gives the Bode plot of the error amplifier.
100 80 60 40 20 45 0 -20 100 1K 10K 100K 1M FREQUENCY 10M 100M 0 GAIN PHASE 90 135 PHASE (Degrees) 180
Figure 3. Internal Oscillator Timing. The frequency of the oscillator is: fOSC = 1 t CHARGE + tDISCHARGE (1) Figure 4. Error Amplifier Open-Loop Gain and Phase vs. Frequency. OUTPUT DRIVERS The ML4828 has four high-current CMOS output drivers, each capable of 1A peak output current. These outputs have been designed to quickly switch the gates of power MOSFET transistors via a gate drive transformer. For higher power applications, the outputs can be connected to external MOSFET drivers. The output phase delay times are set by charging an internal 6.7pF capacitor up to the REF voltage (2.5V) via a current that is externally programmed through RA and R B, for the side A and side B drivers, respectively. The charging current and delay time for side A are given by: (3) IA = 2.5V RA (4) tDA = 6.7pF x R A (6) (7)
The ramp peak is 2.5V and the ramp valley is 1.25V, giving a ramp range of 1.25V. The charging current is set externally through the resistor RT: ICHARGE = 2.5V RT while the discharging current is fixed at 1.4 mA. The charge and discharge times can be determined by: t CHARGE = CT x 1.25V CT x R T = ICHARGE 2 CT x 1.25V CT x 1.25V = IDISCHARGE 1.4mA (2)
tDISCHARGE =
The oscillator frequency can then be found by substituting the results of equations 3 and 4 into equation 1. This frequency activates a T flip-flop which generates the output pulses. The T flip-flop acts as a frequency divider (/2), so the output frequency will be: fOUT = fOSC 2 (5)
The same equations can be applied to RB. For example, with RA = 33k: tDA = 6.7pF x 33k = 220ns (8)
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ML4828
ISWITCH I1 7 CSS TERMINATE PWM CYCLE 20 R1 RSENSE V+ Q C1 ILIM 1V SS V+
+ -
S
IRST 12 RRST CRST 2.5V 1.25V RST
R CLOCK
+ -
INHIBIT OUTPUT UNDER-VOLTAGE LOCKOUT
Figure 5. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
SOFT START TIME CONSTANT During start up, the output voltage is much lower than the steady state value. Without soft start circuitry, the error amplifier output (EAO) would swing all the way to the upper limit and the phase modulator would issue pulses with full duty cycle, possibly causing output overshoot. To ensure smooth start up, EAO (pin 8) is pulled low and then gradually released through the charging of an external soft start capacitor connected to SS (pin 7). The soft start charging current is internally set at 25A. Hence, EAO will rise with a time constant of: dv = 25A dt CSS (9) source IRST. This current charges the reset capacitor C RST. For proper design, RRST should be very large (in the order of 100k). This will cause nearly all of the IRST current (approximately 500A) to go into charging CRST at a rate of: dv = 500A dt CRST (11)
in volts per second. IRST will be turned off at the beginning of the next clock cycle. If the current limit condition is removed, RST will be gradually discharged to ground, and normal operation resumes as shown in Figure 6.
For example, with CSS = 25F, the soft start rate of change will be: dv = 25A = 1V dt 25F s FAULT TIME CONSTANT AND RESTART DELAY Figure 5 shows the internal circuitry and external components involved in fault detection. During normal operation, RST (pin 12) is discharged to ground through the external resistor RRST. The ILIM comparator has a threshold of 1V. RSENSE is selected so that the voltage across it will be equal to the ILIM threshold at the maximum desired ISWITCH current. When the voltage across RSENSE exceeds 1V, the ILIM comparator trips, terminating the present power cycle, and at the same time activating the fault logic to turn on the 500A current (10)
1V V(PIN 20)
2.5V V(PIN 12)
Figure 6. ILIM and Resulting RCRST Waveforms During Load Surge.
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ML4828
If the current limit condition persists, then IRST will be reactivated, thus charging CRST to a higher level as shown in Figure 7. Eventually, the voltage at RST will exceed 2.5V, and the soft start comparator will trip, shutting down all power drivers and inhibiting any further delivery of power. At the same time, the soft start capacitor CSS is discharged to prepare for the next start up cycle.
1V V(PIN 20)
For example, with CRST = 25F and RRST = 240k: dv = 500A = 20 V dt 25F s and tD(RST ) = (240k x 25F) x 1.39 = 8.3s (15) (14)
Since the threshold for shutdown is 2.5V, the controller will shut down after approximately 125ms. After the converter recovers form the current limit condition, the controller will reactivate after 8.3s. UNDERVOLTAGE LOCKOUT During start-up, the ML4828 draws very little current (typically 150A) and VREF is disabled. When VCC rises above 6.0V, the internal circuitry and VREF are enabled, and will stay enabled until VCC falls below the 4.5V UV lockout threshold. SHUTDOWN FUNCTION The ML4828 can be externally shut down by bringing SDN (pin 19) low. The shutdown threshold (VSD) is given by VSD = 0.33 x VCC (16)
2.5V V(PIN 12)
Figure 7. ILIM and Resulting RCRST Waveforms During Short Circuit.
During the ILIM shutdown, IRST is turned off, and CRST is discharged through RRST with a time constant of: tRST = RRST x CRST (12)
When the condition causing the current limit is removed, RRST will discharge CRST with a time constant of tRST. When the voltage at RST (pin 12) drops to 1.25V, the soft start comparator and the converter will undergo a start up cycle. The restart delay (tD(RST)) is given by: tD(RST ) = tRST x 1.39 (13)
For example, if VCC= 5V, then VSD = 1.67V. As long as 2.4V < VCC < 6.0V, the SDN pin will be TTL compatible.
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ML4828
PHYSICAL DIMENSIONS inches (millimeters)
Package: S20 20-Pin SOIC
0.498 - 0.512 (12.65 - 13.00) 20
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.007 - 0.015 (0.18 - 0.38)
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ML4828
PHYSICAL DIMENSIONS inches (millimeters) (Continued)
Package: P20 20-Pin PDIP
1.010 - 1.035 (25.65 - 26.29) 20
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.060 MIN (1.52 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
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ML4828
ORDERING INFORMATION
PART NUMBER ML4828CP ML4828CS ML4828IP ML4828IS TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C -40C to 85C PACKAGE 20-Pin DIP (P20) 20-Pin DIP (S20) (EOL) 20- Pin DIP (P20) (EOL) 20- Pin SOIC (S20) (EOL)
Micro Linear is a registered trademark of Micro Linear Corporation (c) Micro Linear 1997 Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Telex: 275906
DS4828-01
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